
`timescale 1ns / 1ps

module reg_file(
	clk,
	i_wr_en,
	i_a_addr,
	i_b_addr,
	i_b_data,
	o_a_data,
	o_b_data
);

parameter DATA_WIDTH 	= 32;
parameter ADDR_WIDTH 	= 5;
parameter MEM_SIZE		= 32;

input clk;
input i_wr_en;

input [ADDR_WIDTH-1:0] i_a_addr;
input [ADDR_WIDTH-1:0] i_b_addr;

input [DATA_WIDTH-1:0] i_b_data;
output [DATA_WIDTH-1:0] o_a_data;
reg [DATA_WIDTH-1:0] o_a_data;

output [DATA_WIDTH-1:0] o_b_data;
reg [DATA_WIDTH-1:0] o_b_data;


reg [DATA_WIDTH-1:0] mem [0:MEM_SIZE-1];

// read logic - intended latching operation
always@( clk or i_a_addr or i_b_addr )
begin
	if( clk == 1'b1 ) begin
		o_a_data <= mem[ i_a_addr ];
		o_b_data <= mem[ i_b_addr ];
	end
end

// write logic - intended latching operation
always@( clk or i_b_addr or i_b_data or i_wr_en )
begin
	if( clk == 1'b0 ) begin
		if( i_wr_en == 1'b1 )
			mem[ i_b_addr ] <= i_b_data;
	end
end

endmodule
